The present invention relates to sense amplifiers used to sense data in CMOS memory cells, and more specifically, to a latch control circuit within such a sense amplifier.
In an integrated memory circuit, sense amplifiers are used to improve the speed performance of a memory, and to provide signals which conform with the requirements of driving peripheral circuits within the memory. A sense amplifier is an active circuit that reduces the time of signal propagation from an accessed memory cell to the logic circuit at the periphery of the memory cell array, and converts the arbitrary logic levels occurring on a bitline to the digital logic levels of the peripheral circuits. The sensing part of the sense amplifier detects and determines the data content of a selected memory cell. The sensing may be xe2x80x9cnondestructivexe2x80x9d, wherein the data content of the selected memory cell is unchanged, such as in SRAMs, ROMs and PROMs, or the sensing may be xe2x80x9cdestructivexe2x80x9d wherein the data content of the selected memory cell may be altered by the sense operation, such as in DRAMs.
Many sense amplifier circuits include a latch circuit in order to extend the time period during which a bit read from the memory will be available beyond the end of a particular memory cycle. Some sense amplifier circuits use the latch circuit to reduce power consumption by latching the value of the sense amplifier output and then turning off the sensing circuit during time periods when it is idle.
A continuing challenge in designing sense amplifier circuits is to maintain the stability of the voltage level of the output signal. In many sense amplifier circuits, the sense amplifier output node is connected through a CMOS pass gate to the bitline. Therefore, the sense amplifier output is in full electrical communication with the bitline. The latch circuit is usually connected between the sense amplifier output and the bitline. To latch the output, pull-up and pull-down transistors in the last stage of the sense amplifier function to pull up or pull down the voltage value of the bitline. Therefore, the bitline and the sense amplifier output are virtually at the same voltage potential. However, the amount of capacitance at the bitline differs from the amount of capacitance at the sense amplifier output. When the sense amplifier is in its fastest operating mode, the amount of capacitive load on the sense amplifier output is very low. However, the bitline node has several memory cell transistors connected to it, plus additional parasitic capacitance, so the capacitive load on the bitline is much higher than on the sense amplifier output. This factor can affect the stability of the sense amplifier output.
When the latch is activated, the bitline is usually precharged at a value of about one-half of Vcc, where Vcc is the voltage corresponding to a digital logic level of xe2x80x9c1xe2x80x9d or xe2x80x9chighxe2x80x9d. If a logic level of xe2x80x9c1xe2x80x9d was on the sense amplifier output node, then a capacitive partition occurs when the latch is activated. The sense amplifier output could then have a voltage drop which would vary as a function of the number of cells that are connected to the bitline. This occurrence is a transient glitch which causes the sensing circuit to react and pull up the voltage on the sense amp output node back to the logic xe2x80x9c1xe2x80x9d level. However, since there is a brief increment of time before the transient is corrected by the sensing circuit, the transient can potentially cause problems in the operation of the memory cell. In cases in which the sequence timing is critical, the data could be strobed at the same time as when the transient occurs.
This could cause the incorrect data to be read, such that a logic xe2x80x9c1xe2x80x9d, signal could be read as a logic xe2x80x9c0xe2x80x9d signal, or vice versa, and would cause the incorrect data to be processed. Therefore, it is important to attempt to eliminate these transients in order to avoid the erroneous operation of the memory circuit.
It is the object of the present invention to provide a sense amplifier that provides stability to the data latched at the output node and prevents transients that could result in malfunctioning of the memory circuit in which it is used.
It is a further object of the invention to provide a sense amplifier that operates with fast speed and with low power consumption.
The above objects have been achieved by a sense amplifier having a sense line transistor which isolates the sense amplifier output from the impedance of the bitline, thus eliminating or substantially attenuating any transients which may cause erroneous data reads. The sense amplifier also includes an input node for receiving a data signal from a bitline of a memory cell, an output node for producing a sense amp output signal, an enable signal input for receiving an enable signal which triggers circuitry within the sense amplifier, a sensing circuit for sensing the data content of a memory cell and a latching circuit for holding the voltage value of the sense amplifier output. The sense line transistor is connected between the sense amplifier output and the input node in order to increase the strength of the output node and serves to isolate the sense amplifier output from the bitline. Additionally, the sense amplifier of the present invention achieves a power savings because the bitline does not have to be discharged or precharged due to the addition of the sense line transistor. This also helps to improve the speed of the sense amplifier, which is a important factor, as several sense amplifiers would usually be incorporated into a memory circuit.